A series of logic-level pulses can typically be created by performing a logical AND of a continuously running pulse train with a positive logic enable signal. To avoid shortened pulses or glitches at turn-on or turn-off, the enable signal should transition from low to high and high to low when the pulse train is low.
If the phase of the continuously running pulse train is varied, the phase of the enable signal must be varied accordingly. However, the enable signal is typically generated by logic running from a non-adjustable system clock of fixed phase. Consequently, a mechanism is needed for varying the phase of the enable signal so that shortened pulses or glitches are not created.